RM0453 Rev 5 279/1450
RM0453 Power control (PWR)
285
6.6.18 PWR CPU2 control register 3 (PWR_C2CR3)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x084
Reset value: 0x0000 0000
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 LPMS[2:0]: Low-power mode selection for CPU2
These bits are not reset when exiting Standby mode.
These bits select the low-power mode entered when CPU2 enters the Deep-Sleep mode.
The system low-power mode entered depends also on the PWR_CR1.LPMS[2:0] allowed
Low-power mode from CPU1.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode must be entered
instead of Stop 2.
In Standby mode, SRAM2 is preserved, depending on RRS bit configuration in PWR
control register 3 (PWR_CR3).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
EIWUL Res.
EWRFI
RQ
Res.
EWRB
USY
APC Res.
EWPV
D
Res. Res. Res. Res. Res.
EWUP
3
EWUP
2
EWUP
1
rw rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 EIWUL: internal wake-up line for CPU2 enable
0: Internal wake-up line to CPU2 disabled
1: Internal wake-up line to CPU2 enabled
Bit 14 Reserved, must be kept at reset value.
Bit 13 EWRFIRQ: radio IRQ[2:0] wake-up for CPU2 enable
When this bit is set, the radio IRQ[2:0] is enabled and triggers a wake-up from Standby event
to CPU2.
Bit 12 Reserved, must be kept at reset value.
Bit 11 EWRBUSY: radio busy wake-up for CPU2 enable
When this bit is set, the radio busy is enabled and triggers a wake-up from Standby event to
CPU2 when a rising or a falling edge occurs. The active edge is configured via the
WRFBUSYP bit in the PWR control register 4 (PWR_CR4).
To Next Page
Loading...
Need help?
General
