STMicroelectronics STM32WL5 Series - PWR Control Register 4 (PWRCR4)

Power control (PWR) RM0453
268/1450 RM0453 Rev 5
6.6.4 PWR control register 4 (PWR_CR4)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x00C
Reset value: 0x0000 0000
Bit 2 EWUP3: Wake-up pin WKUP3 for CPU1 enable
When this bit is set, the external wake-up pin WKUP3 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU1. The active edge is configured via the WP3 bit in the PWR control register 4
(PWR_CR4).
Bit 1 EWUP2: Wake-up pin WKUP2 for CPU1 enable
When this bit is set, the external wake-up pin WKUP2 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU1. The active edge is configured via the WP2 bit in the PWR control register 4
(PWR_CR4).
Bit 0 EWUP1: Wake-up pin WKUP1 for CPU1 enable
When this bit is set, the external wake-up pin WKUP1 is enabled and triggers an interrupt
and wake-up from Stop, Standby or Shutdown event when a rising or a falling edge occurs to
CPU1. The active edge is configured via the WP1 bit in the PWR control register 4
(PWR_CR4).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
C2BOOT
Res. Res. Res.
WRFBUSYP
Res. VBRS VBE Res. Res. Res. Res. Res. WP3 WP2 WP1
rw rw rw rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 C2BOOT: CPU2 boot after reset or wake-up from Stop or Standby mode
0: No CPU2 boot after reset or wake-up from Stop or Standby mode
1: CPU2 boot after reset and after wake-up from Stop or Standby mode, when there is a
CPU2 wake-up event
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 WRFBUSYP: Wake-up radio busy polarity
This bit defines the polarity used for an event detection on radio busy signal.
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 10 Reserved, must be kept at reset value.