RM0453 Rev 5 1413/1450
RM0453 Debug support (DBG)
1435
38.12.8 DBGMCU CPU2 APB2 peripheral freeze register
(DBGMCU_C2APB2FZR)
Address offset: 0x048
Reset value: 0x0000 0000
38.12.9 DBGMCU register map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
TIM17
_STOP
DBG_
TIM16
_STOP
Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res.
DBG_
TIM1
_STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 stop in CPU2 debug
0: Normal operation. TIM17 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM17 is frozen while CPU2 is in debug mode.
Bit 17 DBG_TIM16_STOP: TIM16 stop in CPU2 debug
0: Normal operation. TIM16 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM16 is frozen while CPU2 is in debug mode.
Bits 16:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 stop in CPU2 debug
0: Normal operation. TIM1 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM1 is frozen while CPU2 is in debug mode.
Bits 10:0 Reserved, must be kept at reset value.
Table 282. DBGMCU register map and reset values
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
DBGMCU_
IDCODER
REV_ID[15:0]
Res.
Res.
Res.
Res.
DEV_ID[11:0]
Reset value xxxxxxxxxxxxxxxx 010010010111
0x004
DBGMCU_CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DBG_STANDBY
DBG_STOP
DBG_SLEEP
Reset value 000
0x008-
0x038
Reserved Reserved.
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