Debug support (DBG) RM0453
1412/1450 RM0453 Rev 5
38.12.7 DBGMCU CPU1 APB2 peripheral freeze register
(DBGMCU_APB2FZR)
Address offset: 0x04C
Reset value: 0x0000 0000
Bit 5 DBG_LPTIM2_STOP: LPTIM2 stop in CPU2 debug
0: Normal operation. LPTIM2 continues to operate while CPU2 is in debug mode.
1: Stop in debug. LPTIM2 is frozen while CPU2 is in debug mode.
Bits 4:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG_
TIM17
_STOP
DBG_
TIM16
_STOP
Res.
rw rw
1514131211109876543210
Res. Res. Res. Res.
DBG_
TIM1
_STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 DBG_TIM17_STOP: TIM17 stop in CPU1 debug
0: Normal operation. TIM17 continues to operate while CPU1 is in debug mode.
1: Stop in debug. TIM17 is frozen while CPU1 is in debug mode.
Bit 17 DBG_TIM16_STOP: TIM16 stop in CPU1 debug
0: Normal operation. TIM16 continues to operate while CPU1 is in debug mode.
1: Stop in debug. TIM16 is frozen while CPU1 is in debug mode.
Bits 16:12 Reserved, must be kept at reset value.
Bit 11 DBG_TIM1_STOP: TIM1 stop in CPU1 debug
0: Normal operation. TIM1 continues to operate while CPU1 is in debug mode.
1: Stop in debug. TIM1 is frozen while CPU1 is in debug mode.
Bits 10:0 Reserved, must be kept at reset value.
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