RM0453 Rev 5 1051/1450
RM0453 Inter-integrated circuit (I2C) interface
1113
34.4.1 I2C block diagram
The block diagram of the I2C interface is shown in Figure 276.
Figure 276. I2C block diagram
The I2C is clocked by an independent clock source, which allows the I2C to operate
independently from the PCLK frequency.
For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 34.3: I2C implementation.
MSv46198V2
I2CCLK
Wake-up
on
address
match
SMBUS
PEC
generation/
check
Shift register
Data control
SMBus
timeout
check
Clock control
Master clock
generation
Slave clock
stretching
SMBus alert
control/status
Digital
noise
filter
I2C_SCL
I2C_SMBA
Registers
APB bus
GPIO
logic
Analog
noise
filter
Digital
noise
filter
I2C_SDA
GPIO
logic
Analog
noise
filter
i2c_pclk
i2c_ker_ck
PCLK
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