RM0453 Rev 5 79/1450
RM0453 Global security controller (GTZC)
97
Application information
The TZSC and TZIC sub-blocks can be used in one of the following ways:
• programmed during secure boot only, locked and not changed afterwards
• dynamically re-programmed when using specific application code or secure kernel
(microvisor). When not locked, MPC area size for non-secure memories can be
changed by privileged software executing in privileged mode, and secure memories
can only be changed by privileged software executing in privileged mode in the secure
world. Same remark applies to the SECCFGR1 and PRIVCFGR1 registers inside
TZSC, that define secure and privileged protection level for each peripheral.
The STM32 security architecture with secure, securable and security-aware peripherals is
shown in the figure below.
Figure 4. GTZC security architecture
3.4 GTZC functional description
3.4.1 GTZC block diagram
Figure 5 describes the combined feature of TZSC and TZIC. Each sub-block is controlled by
its own AHB configuration port. TZSC defines which peripheral is secured and/or privileged.
TZIC centralizes the illegal access events.
When the device is non-secure (ESE = 0), TZIC has no function, memories are non-secure
and unprivileged and illegal interrupts are disabled. Peripherals can still be made privileged.
MSv60798V2
AHB
GTZC
Securable peripherals
CPU1
SPI3
AHB2AP
B
APB
MPCWM
tzsc_periph_ priv
AHB-PPC
STUB
Sec-gate
Securable memories
Master sec/priv
TZIC
Privileged
Unprivileged
SRAM1
tzsc_periph sec/priv
TZSC
RNG
MPCWM
Privileged
Crypto
(AES)
Unprivileged
SRAM2
MPCWM
Privileged
Unprivileged
Flash
CPU2
Master priv
DMA/DMAMUX
Master sec/priv
AHB-
PPC
STUB
tzsc_periph sec/priv
ila events
n
tzic_ila_it
tzsc_periph[n] sec
tzsc_mpcwm[n] sec
tzsc_ila_ event
tzsc_mpcwm_priv
tzsc_mpcwm_priv
PKA
AHB-
PPC
STUB
tzsc_periph sec/priv
tzsc_mpcwm_priv
Non-secure
Secure
Security-aware
Secure
Security-
aware
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