RM0453 Rev 5 513/1450
RM0453 Extended interrupts and event controller (EXTI)
524
For configurable event inputs, when the enabled edges occur on the event input, an event
request is generated. When the associated it_exti_per(y) interrupt is unmasked, the
corresponding pending bit in EXTI_PR is set, the CPU sub-system wakes up and the CPU
interrupt signal is activated. The EXTI_PR pending bit must be set to 1 by software. This
clears the it_exti_per(y) interrupt.
For direct event inputs, when enabled in the associated peripheral, an event request is
generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.
When the associated direct event is unmasked in EXTI_IM, the corresponding CPU sub-
system wakes up. The CPU is woken up (interrupted) by the peripheral synchronous
interrupt.
The CPU event must be unmasked in EXTI_EMR to generate an event. When the enabled
edges occur on the event input, a CPU event pulse is generated. There is no event pending
bit.
For the configurable event inputs, an event request can be generated by software, setting to
1 the corresponding bit in the interrupt/event register EXTI_SWIER. This allows the
generation of a rising edge on the event. The edge event pending bit must be set in
EXTI_PR, irrespective of the setting in EXTI_RTSR.
16.6 EXTI registers
The EXTI register map is divided in sections listed in the table below.
All these registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.
1
0 Status latched Yes Masked Yes
(2)
1 Status latched Yes Yes Yes
1. The single it_exti_per(y) interrupt goes to both CPUs. If no interrupt is required for the CPUn, the it_exti_per(y) interrupt
must be masked in the CPUn NVIC.
2. Only if the CPU interrupt is enabled in EXTI_CnIMRm.IMb.
Table 95. Masking functionality (continued)
CPU interrupt enable
EXTI_CnIMRm.IMb
CPU event enable
EXTI_CnEMRm.EMb
Configurable
event inputs
EXTI_PRm.PIFb
it_exti_per(y)
(1)
CPUn event
CPUn
wake-up
Table 96. EXTI register map sections
Address Description
0x000 - 0x01C General configurable event [31:0] configuration
0x020 - 0x03C General configurable event [63:32] configuration
0x080 - 0x0BC CPU1 input event configuration
0x0C0 - 0x0FC CPU2 input event configuration
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