Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0453
1134/1450 RM0453 Rev 5
The causes which contribute to the total deviation are:
• DTRA: deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
• DQUANT: error due to the baud rate quantization of the receiver
• DREC: deviation of the receiver local oscillator
• DTCL: deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
where
DWU is the error due to sampling point deviation when the wake-up from low-
power mode is used.
when M[1:0] = 01:
when M[1:0] = 00:
when M[1:0] = 10:
t
WUUSART
is the time between the detection of the start bit falling edge and the
instant when the clock (requested by the peripheral) is ready and reaching the
peripheral, and the regulator is ready.
The USART receiver can receive data correctly at up to the maximum tolerated deviation
specified in Table 241, Table 242, depending on the following settings:
• 9-, 10- or 11-bit character length defined by the M bits in the USART_CR1 register
• Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
• Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.
• Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register.
Table 241. Tolerance of the USART receiver when BRR [3:0] = 0000
M bits
OVER8 bit = 0 OVER8 bit = 1
ONEBIT = 0 ONEBIT = 1 ONEBIT = 0 ONEBIT = 1
00 3.75% 4.375% 2.50% 3.75%
01 3.41% 3.97% 2.27% 3.41%
10 4.16% 4.86% 2.77% 4.16%
DTRA DQUANT DREC DTCL DWU++++USART receiver tolerance<
DWU
t
WUUSART
11 Tbit×
---------------------------=
DWU
t
WUUSART
10 Tbit×
---------------------------=
DWU
t
WUUSART
9Tbit×
---------------------------=
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