RM0453 Rev 5 1351/1450
RM0453 Debug support (DBG)
1435
Refer to Section 38.8: CPU1 ROM table and Section 38.13: CPU2 ROM tables for the
register boundary addresses.
38.7 Cross trigger interface (CTI) and cross trigger matrix (CTM)
CTI and CTM taken together form the CoreSight embedded cross trigger (see Figure 388).
There are two CTI components, one dedicated to the CPU2 and one dedicated to the
CPU1. The CTIs are connected to each other via the CTM. The CTI registers are accessible
to the debugger via the corresponding access port and associated AHB.
Figure 388. Embedded cross trigger
The CTIs enable events from various sources to trigger debug activity. For example, a
breakpoint reached in one of the processor cores can stop the other processor.
Each CTI has up to eight trigger inputs and eight trigger outputs. Any input can be
connected to any output, on the same CTI or on another CTI via the CTM.
The trigger input and output signals for each CTI are listed in Table 272 to Table 275.
0xFFC
DWT_CIDR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[27:20]
Reset value 10110001
Table 271. DWT register map and reset values (continued)
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 272. CPU2 CTI inputs
No. Source signal Source component Comments
0 HALTED CPU2 CPU2 halted - Indicates CPU2 is in debug mode.
1 - - Not used
MSv60369V2
AHB
Cortex
®
-M0+ CTI
Cortex
®
-M0+
CPU
HALTED
EDBGRQ
DBGRESTART
PPB
Cortex
®
-M4 CTI
Cortex
®
-M4
CPU
HALTED
EDBGRQ
CTM channels [3:0]
TRIGIN0
TRIGOUT0
TRIGOUT7
TRIGIN0
TRIGOUT0
DBGRESTART
TRIGOUT7
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