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STMicroelectronics STM32WL5 Series

STMicroelectronics STM32WL5 Series
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RM0453 Rev 5 1067/1450
RM0453 Inter-integrated circuit (I2C) interface
1113
Slave receiver
RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is
set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.
When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an
interrupt is generated.
Figure 286. Transfer sequence flow for slave receiver with NOSTRETCH = 0
MS19855V2
Slave initialization
Slave reception
Read ADDCODE and DIR in I2C_ISR
Set I2C_ICR.ADDRCF
Write I2C_RXDR.RXDATA
I2C_ISR.ADDR
=1?
No
Yes
I2C_ISR.RXNE
=1?
Yes
No
SCL
stretched

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