STMicroelectronics STM32WL5 Series User Manual

Inter-processor communication controller (IPCC) RM0453
388/1450 RM0453 Rev 5
Once the sending processor has posted the communication data in the memory, it sets the
channel status flag CHnF to occupied with CHnS.
Once the receiving processor has retrieved the communication data from the memory, it
clears the channel status flag CHnF back to free with CHnC.
Figure 37. IPCC Simplex channel mode transfer timing
Table 68. Bits used for the communication
Processor A B
SEND A = 1
RECEIVE B = 2
IPCC_C1CR.TXFIE
IPCC_C1MR.CHnFM
IPCC_C1SCR.CHnS
IPCC_C1TOC2SR.CHnF
IPCC_C2CR.RXOIE
IPCC_C2MR.CHnOM
IPCC_C2SCR.CHnC
SEND A = 2
RECEIVE B = 1
IPCC_C2CR.TXFIE
IPCC_C2MR.CHnFM
IPCC_C2SCR.CHnS
IPCC_C2TOC1SR.CHnF
IPCC_C1CR.RXOIE
IPCC_C1MR.CHnOM
IPCC_C1SCR.CHnC
MS42430V1
Processor A
Processor B
CHnF
TX free interrupt
RX occupied interrupt
Write
communication
data
Memory occupation
Communication data
Read
communication
data
Communication data
Write
communication
data

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English