Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0453
1284/1450 RM0453 Rev 5
Figure 366. Transmitting 0x8EAA33
• In reception mode:
If data 0x8EAA33 is received:
Figure 367. Receiving 0x8EAA33
Figure 368. I
2
S Philips standard (16-bit extended to 32-bit packet frame)
When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format.
If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the
operation shown in Figure 369 is required.
Figure 369. Example of 16-bit data frame extended to 32-bit channel frame
MS19593V2
0x8EAA 0x33XX
First write to Data register Second write to Data register
Only the 8 MSBs are sent
to compare the 24 bits.
8 LSBs have no meaning
and can be anything
MS19594V1
0x8EAA 0x33XX
First read to Data register Second read to Data register
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything
MS19599V1
CK
WS
SD
Transmission
Reception
16-bit data
MSB
LSB
Channel left 32-bit
Channel right
16-bit remaining 0 forced
MS19595V1
0x76A3
Only one access to SPIx_DR
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