STMicroelectronics STM32WL5 Series User Manual

RM0453 Rev 5 1373/1450
RM0453 Debug support (DBG)
1435
Figure 391. CPU1 CoreSight topology
38.8.1 CPU1 ROM memory type register (ROM_MEMTYPER)
Address offset: 0xFCC
Reset value: 0x0000 0001
MSv60373V2
CPU1 ROM table
@0xE00FF000
System control space (SCS)
@0xE000E000
0xE00FF000
AHB-AP
AP_BASER register
(0xF8)
Register file base0x000
PIDR40xFD0
CIDR30xFFC
Register file base
Breakpoint unit (FPB)
@0xE0002000
0x000
PIDR40xFD0
CIDR30xFFC
Register file base
Trace port interface (TPIU)
@0xE0040000
0x000
PIDR40xFD0
CIDR30xFFC
Register file base
Data watchpoint/trace (DWT)
@0xE0001000
0x000
PIDR40xFD0
CIDR30xFFC
Register file base
Instrumentation trace (ITM)
@0xE0000000
0x000
PIDR40xFD0
CIDR30xFFC
Offset: 0xFFF0F0000x000
Offset: 0xFFF020000x004
Offset: 0xFFF030000x008
Offset: 0xFFF010000x00C
PIDR40xFD0
CIDR30xFFC
0x010 Offset: 0xFFF41000
Top of table0x018
0x014
Register file base
Cross trigger (CTI)
@0xE0043000
0x000
PIDR40xFD0
CIDR30xFFC
Offset: 0xFFF44000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
151413121110987654321 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSMEM
r
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 SYSMEM: system memory
1: System memory present on this bus

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English