General-purpose timer (TIM2) RM0453
860/1450 RM0453 Rev 5
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 230. Control circuit in external clock mode 2 + trigger mode
26.3.19 Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 231: Master/Slave timer example and Figure 232: Master/slave connection example
with 1 channel only timers present an overview of the trigger selection and the master mode
selection blocks.
Figure 231. Master/Slave timer example
MS33110V1
34 35 36
TIF
Counter register
Counter clock = CK_CNT = CK_PSC
ETR
CEN/CNT_EN
TI1
MS32694V1
Counter
Master
mode
control
UEV
Prescaler
Clock
Slave
mode
control
CounterPrescaler
CK_PSCITR1TRGO1
MMS
SMS
TS
Input
trigger
selection
TIM1
TIM2
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