RM0453 Rev 5 1287/1450
RM0453 Serial peripheral interface / integrated interchip sound (SPI/I2S)
1311
Figure 375. Operations required to transmit 0x3478AE
• In reception mode:
If data 0x3478AE are received, two successive read operations from the SPIx_DR
register are required on each RXNE event.
Figure 376. Operations required to receive 0x3478AE
Figure 377. LSB justified 16-bit extended to 32-bit packet frame
When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it
corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in Figure 378 is required.
0xXX34
0x78AE
First write to Data register
conditioned by TXE=1
Second write to Data register
conditioned by TXE=1
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
MS19596V1
0xXX34
0x78AE
First read from Data register
conditioned by RXNE=1
Second read from Data register
conditioned by RXNE=1
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
MS19597V1
MS30105V1
CK
WS
SD
Transmission
Reception
16-bit data
0 forced
MSB
LSB
Channel left 32-bit
Channel right
16-bit remaining
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