STMicroelectronics STM32WL5 Series

RM0453 Rev 5 1055/1450
RM0453 Inter-integrated circuit (I2C) interface
1113
Figure 278. Setup and hold timings
When the SCL falling edge is internally detected, a delay (
t
SDADEL
, impacting the hold time
t
HD;DAT
) is inserted before sending SDA output: t
SDADEL
= SDADEL x t
PRESC
+ t
I2CCLK
, where
t
PRESC
= (PRESC + 1) x t
I2CCLK
.
The total SDA output delay is:
t
SYNC1
+ {[SDADEL x (PRESC + 1) + 1] x t
I2CCLK}
t
SYNC1
duration depends upon:
– SCL falling slope
– When enabled, input delay brought by the analog filter: t
AF(min)
< t
AF
< t
AF(max)
– When enabled, input delay brought by the digital filter: t
DNF
= DNF x t
I2CCLK
– Delay due to SCL synchronization to I2CCLK clock (two to three I2CCLK periods)
To bridge the undefined region of the SCL falling edge, the user must program SDADEL in
such a way that:
{t
f (max)
+ t
HD;DAT (min)
- t
AF(min)
- [(DNF + 3) x t
I2CCLK
]} / {(PRESC + 1) x t
I2CCLK
} ≤ SDADEL
SDADEL ≤ {t
HD;DAT (max)
- t
AF(max)
- [(DNF + 4) x t
I2CCLK
]} / {(PRESC + 1) x t
I2CCLK
}
MSv40108V1
t
SYNC1
SCL falling edge internal
detection
SDADEL: SCL stretched low by the I2C
SDA output delay
SCL
SDA
DATA HOLD TIME
t
HD;DAT
SCLDEL
SCL stretched low by the I2C
SCL
SDA
DATA SETUP TIME
t
SU;STA
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output.
MS49608V1
t
SYNC1
SCL falling edge internal
detection
SDADEL: SCL stretched low by the I2C
SDA output delay
SCL
SDA
DATA HOLD TIME
t
HD;DAT
SCLDEL
SCL stretched low by the I2C
SCL
SDA
DATA SETUP TIME
t
SU;DAT
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output.