STMicroelectronics STM32WL5 Series User Manual

RM0453 Rev 5 265/1450
RM0453 Power control (PWR)
285
6.6.2 PWR control register 2 (PWR_CR2)
This register is reset when exiting the Standby mode.
Address offset: 0x004
Reset value: 0x0000 0000
Bit 4 FPDR: Flash memory power-down mode during LPRun for CPU1
This bit can only be written to 1 after unlocking this register bit, by first writing (code 0xC1B0)
into this register (when writing the code, the register bits are not updated). Selects whether
the flash memory is in power-down mode or Idle mode when in LPRun mode. (flash memory
can only be in power-down mode when code is executed from SRAM). Flash memory is only
set in power-down mode when the system is in LPRun mode, and the PWR_C2CR1.FPDR
bit from CPU2 also allows so.
0: Flash memory in Idle mode when system is in LPRun mode
1: Flash memory in Power-down mode when system is in LPRun mode
Bit 3 SUBGHZSPINSSSEL: sub-GHz SPI NSS source select
This bit is set and cleared by software.
0: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS
functionality enabled)
1: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)
Bits 2:0 LPMS[2:0]: Low-power mode selection for CPU1
These bits are not reset when exiting Standby mode.
These bits select the low-power mode allowed when CPU1 enters the Deep -Sleep mode.
The system low-power mode entered depends also on the PWR_C2CR1.LPMS[2:0] allowed
low-power mode from CPU2.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode must be entered
instead of Stop 2.
In Standby mode, SRAM2 is preserved, depending on RRS bit configuration in
PWR_CR3.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. PVME3 Res. Res. PLS[2:0] PVDE
rw rw rw rw rw
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 PVME3: Peripheral voltage monitoring 3 enable:
V
DDA
versus 1.62 V
0: PVM3 (
V
DDA
monitoring versus 1.62 V threshold) disable.
1: PVM3 (
V
DDA
monitoring versus 1.62 V threshold) enable.
Bits 5:4 Reserved, must be kept at reset value.

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English