RM0453 Rev 5 1337/1450
RM0453 Debug support (DBG)
1435
38.5.6 AP identification register (AP_IDR)
Address offset: 0xFC
Reset value: 0x2477 0011 (AP0)
Reset value: 0x6477 0001 (AP1)
38.5.7 AP register map and reset values
These registers are not on the CPU memory bus and are only accessed through SW-DP
and JTAG-DP debug interface.
The access port address is 8-bit wide, defined by debug port register
DP_SELECTR.APBANKSEL[3:0] field and by JTAG-DP register DPACC or SW-DP packet
request A[3:2] field.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REVISION[3:0] JEDECBANK[3:0] JEDECCODE[6:0]
MEMA
P
rrrrrrrrrrrrrrrr
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. IDENTITY[7:0]
rrrrrrrr
Bits 31:28 REVISION[3:0]: revision
0x2: CPU1 Cortex-M4 r0p3
0x6: CPU2 Cortex-M0+ r0p7
Bits 27:24 JEDECBANK[3:0]: JEDEC bank
0x4: Arm
Bits 23:17 JEDECCODE[6:0]: JEDEC code
0x3B: Arm
Bit 16 MEMAP: memory access port
0x1: Standard register map
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IDENTITY[7:0]: AP type
0x11: CPU1 (Cortex-M4) AHB-AP (AP0)
0x01: CPU2 (Cortex-M0+) AHB-AP (AP1)
Others: reserved
Table 270. AP register map and reset values
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
AP_CSWR
Res.
SPROT
Res.
PROT[4:0]
SPISTATUS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MODE[3:0]
TRINPROG
DEVICEEN
ADDRINC[1:0]
Res.
SIZE[2:0]
Reset value 0 000110 00000100 000
0x04
AP_TAR TA[31:0]
Reset value 00000000000000000000000000000000
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