STMicroelectronics STM32WL5 Series

Sub-GHz radio (SUBGHZ) RM0453
210/1450 RM0453 Rev 5
5.10.9 Sub-GHz radio generic CFO LSB register (SUBGHZ_GCFORL)
Address offset: 0x6B1
Reset value: 0x00
5.10.10 Sub-GHz radio generic packet control 1 register
(SUBGHZ_GPKTCTL1R)
Address offset: 0x06B4
Reset value: 0x04
This register must be cleared to 0x00 when using packet types other than LoRa.
5.10.11 Sub-GHz radio generic packet control 1A register
(SUBGHZ_GPKTCTL1AR)
Address offset: 0x6B8
Reset value: 0x21
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 DEMOD_CFO[3:0]: actual frequency error from normalized value (MSB bits)
76543210
DEMOD_CFO[7:0]
rrrrrrrr
Bits 7:0 DEMOD_CFO[7:0]: actual frequency error from normalized value (LSB bits)
76543210
Res Res Res Res Res PBDETON PBDETLEN[1:0]
rw rw rw
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 PBDETON: Preamble detection enable
Bits 1:0 PBDETLEN: Receiver preamble detection length
0b00: 8-bit preamble detection
0b01: 16-bit preamble detection
0b10: 24-bit preamble detection
0b11: 32-bit preamble detection
76543210
Res. Res. SYNCDETEN CONTTX INFSEQSEL[1:0] INFSQEQEN WHITEINI[8]
rw rw rw rw rw rw
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 SYNCDETEN: Generic packet synchronization word detection enable