STMicroelectronics STM32WL5 Series

Inter-integrated circuit (I2C) interface RM0453
1070/1450 RM0453 Rev 5
Figure 289. Master clock generation
MS19858V1
t
SYNC1
SCL high level detected
SCLH counter starts
SCLH
SCL
SCL master clock generation
SCL released
SCL low level detected
SCLL counter starts
SCL driven low
SCLL
t
SYNC2
SCL master clock synchronization
SCLL
SCL driven low by
another device
SCL low level detected
SCLL counter starts
SCL released
SCLH
SCLH
SCL high level detected
SCLH counter starts
SCL high level detected
SCLH counter starts
SCL low level detected
SCLL counter starts
SCLL
SCL driven low by
another device
SCLH
SCL high level detected
SCLH counter starts