STMicroelectronics STM32WL5 Series

AES hardware accelerator (AES) RM0453
682/1450 RM0453 Rev 5
Note: AES is not disabled after a WRERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 23.5: AES interrupts.
The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.
23.5 AES interrupts
Individual maskable interrupt sources generated by the AES peripheral signal the following
events:
• computation completed
• read error
• write error
These sources are combined into a common interrupt signal from the AES peripheral that
connects to the Arm
®
Cortex
®
interrupt controller. Each can individually be
enabled/disabled, by setting/clearing the corresponding enable bit of the AES_CR register,
and cleared by setting the corresponding bit of the AES_CR register.
The status of each can be read from the AES_SR register.
Table 139 gives a summary of the interrupt sources, their event flags and enable bits.
23.6 AES processing latency
The tables below summarize the latency to process a 128-bit block for each mode of
operation.
Table 139. AES interrupt requests
Interrupt
acronym
AES
interrupt event Event flag Enable bit
Interrupt clear
method
AES computation completed flag CCF CCFIE set CCFC
(1)
read error flag RDERR
ERRIE set ERRC
(1)
write error flag WRERR
1. Bit of the AES_CR register.
Table 140. Processing latency for ECB, CBC and CTR
Key size Mode of operation Algorithm
Clock
cycles
128-bit
Mode 1: Encryption ECB, CBC, CTR 51
Mode 2: Key derivation - 59
Mode 3: Decryption ECB, CBC, CTR 51
256-bit
Mode 1: Encryption ECB, CBC, CTR 75
Mode 2: Key derivation - 82
Mode 3: Decryption ECB, CBC, CTR 75