Inter-integrated circuit (I2C) interface RM0453
1084/1450 RM0453 Rev 5
Figure 299. Timeout intervals for t
LOW:SEXT
, t
LOW:MEXT
.
Bus idle detection
A master can assume that the bus is free if it detects that the clock and data signals have
been high for t
IDLE
greater than t
HIGH
,
MAX
(refer to Table 226).
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.
34.4.12 SMBus initialization
This section is relevant only when SMBus feature is supported (see Section 34.3).
In addition to I2C initialization, some other specific initialization must be done to perform
SMBus communication.
Received command and data acknowledge control (slave mode)
A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave byte control mode must be enabled by setting the
SBC bit in the I2C_CR1 register. Refer to Slave byte control mode for more details.
Specific address (slave mode)
The specific SMBus addresses must be enabled if needed. Refer to Bus idle detection for
more details.
• The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2C_CR1 register.
• The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2C_CR1 register.
• The alert response address (0b0001100)
is enabled by setting the ALERTEN bit in the
I2C_CR1 register.
MS19866V1
Start Stop
t
LOW:SEXT
t
LOW:MEXT
t
LOW:MEXT
t
LOW:MEXT
Clk
Ack
Clk
Ack
SMBCLK
SMBDAT
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