STMicroelectronics STM32WL5 Series User Manual

RM0453 Rev 5 683/1450
RM0453 AES hardware accelerator (AES)
694
23.7 AES registers
23.7.1 AES control register (AES_CR)
Address offset: 0x00
Reset value: 0x0000 0000
Table 141. Processing latency for GCM and CCM (in clock cycles)
Key size Mode of operation Algorithm Init Phase
Header
phase
(1)
Payload
phase
(1)
Tag phase
(1)
128-bit
Mode 1: Encryption/
Mode 3: Decryption
GCM64355159
CCM 63 55 114 58
256-bit
Mode 1: Encryption/
Mode 3: Decryption
GCM88357575
CCM 87 79 162 82
1. Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. NPBLB[3:0] Res.
KEYSIZE
Res.
CHMOD[2]
rw rw rw rw rw rw
1514131211109876543210
Res. GCMPH[1:0]
DMAOUTEN
DMAINEN
ERRIE CCFIE ERRC CCFC CHMOD[1:0] MODE[1:0] DATATYPE[1:0] EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 NPBLB[3:0]: Number of padding bytes in last block
The bitfield sets the number of padding bytes in last block of payload:
0000: All bytes are valid (no padding)
0001: Padding for one least-significant byte of last block
...
1111: Padding for 15 least-significant bytes of last block
Bit 19 Reserved, must be kept at reset value.
Bit 18 KEYSIZE: Key size selection
This bitfield defines the length of the key used in the AES cryptographic core, in bits:
0: 128
1: 256
Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write
access and it is not cleared by that write access.
Bit 17 Reserved, must be kept at reset value.
Bit 15 Reserved, must be kept at reset value.

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English