RM0453 Rev 5 137/1450
RM0453 Embedded flash memory (FLASH)
154
4.10.8 FLASH option register (FLASH_OPTR)
Address offset: 0x020
Reset value: 0x3FFF F0AA
Default reset value from ST production is given. Subsequently, 0bXX11 XXXX X111 XXXX
1XXX XXXX XXXX XXXX, the option bits are loaded with user values from the flash
memory at reset release.
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register can only be written by the CPU1 in RDP level 0 or RDP level 1.
When the system is secure (ESE = 1), this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
access is ignored and an illegal access event is generated. Unprivileged read access is still
allowed.
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SYSF_ECC: system flash memory ECC fail
This bit indicates that the ECC error correction or double ECC error detection is located in
the system flash memory.
Bits 19:17 Reserved, must be kept at reset value.
Bits 16:0 ADDR_ECC[16:0]: ECC fail double-word address
This bit indicates that double-word address is concerned by the ECC error correction or
causes the double ECC error detection.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C2BOOT_LOCK
BOOT_
LOCK
Res. Res.
nBOOT0
nSWBOOT0
SRAM_RST
SRAM2_PE
nBOOT1
Res. Res. Res.
WWDG
_SW
IWDG_
STDBY
IWDG_
STOP
IWDG_
SW
rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res.
nRST_
SHDW
nRST_
STDBY
nRST_
STOP
BOR_LEV[2:0] ESE RDP[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
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