RM0453 Rev 5 269/1450
RM0453 Power control (PWR)
285
6.6.5 PWR status register 1 (PWR_SR1)
This register is not reset when exiting Standby modes.
Access: two additional APB cycles are needed to read this register versus a standard APB
read.
Address offset: 0x010
Reset value: 0x0000 0000
Bit 9 VBRS: V
BAT
battery charging resistor selection
0: V
BAT
charging through a 5 kΩ resistor
1: V
BAT
charging through a 1.5 kΩ resistor
Bit 8 VBE: V
BAT
battery charging enable
0: V
BAT
battery charging disabled
1: V
BAT
battery charging enabled
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 WP3: Wake-up pin WKUP3 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 1 WP2: Wake-up pin WKUP2 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 0 WP1: Wake-up pin WKUP1 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
WUFI C2HF Res. Res.
WRFBUSYF
Res. Res.
WPVDF
Res. Res. Res. Res. Res. WUF3 WUF2 WUF1
rr r r rrr
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 WUFI: Internal wake-up interrupt flag
This bit is set when a wake-up is detected on the internal wake-up line. It is cleared when all
internal wake-up sources are cleared.
Bit 14 C2HF: CPU2 hold interrupt flag
This bit is set when a CPU2 wake-up is detected (except an illegal access wake-up) when
C2BOOT = 0. It is cleared by PWR_SCR.CC2HF.
Bits 13:12 Reserved, must be kept at reset value.
To Next Page
Loading...
Need help?
General
