STMicroelectronics STM32WL5 Series

Debug support (DBG) RM0453
1352/1450 RM0453 Rev 5
2 - - Not used
3 - - Not used
4 - - Not used
5 - - Not used
6 - - Not used
7 - - Not used
Table 273. CPU2 CTI outputs
No. Output signal Destination component Comments
0 EDBGRQ CPU2 CPU2 halt request - Puts CPU2 in debug mode.
1 - - Not used
2 - - Not used
3 - - Not used
4 - - Not used
5 - - Not used
6 - - Not used
7 DBGRESTART CPU2 CPU2 restart request - CPU2 exits debug mode.
Table 274. CPU1 CTI inputs
No. Source signal Source component Comments
0 HALTED CPU1 CPU1 halted - indicates CPU1 is in debug mode.
1 - - Not used
2 - - Not used
3 - - Not used
4 - - Not used
5 - - Not used
6 - - Not used
7 - - Not used
Table 275. CPU1 CTI outputs
No. Source signal Source component Comments
0 EDBGRQ CPU1 CPU1 halt request - Puts CPU1 in debug mode.
1 - - Not used
2 - - Not used
Table 272. CPU2 CTI inputs (continued)
No. Source signal Source component Comments