RM0453 Rev 5 595/1450
RM0453 Digital-to-analog converter (DAC)
616
19.4.3 DAC channel enable
The DAC channel can be powered on by setting its corresponding EN1 bit in the DAC_CR
register. The DAC channel is then enabled after a t
WAKEUP
startup time.
Note: The EN1 bit enables the analog DAC channel1 only. The DAC channel1 digital interface is
enabled even if the EN1 bit is reset.
19.4.4 DAC data format
Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
• Single DAC channel
There are three possibilities:
– 8-bit right alignment: the software has to load data into the DAC_DHR8R1[7:0] bits
(stored into the DHR1[11:4] bits)
– 12-bit left alignment: the software has to load data into the DAC_DHR12L1 [15:4]
bits (stored into the DHR1[11:0] bits)
– 12-bit right alignment: the software has to load data into the DAC_DHR12R1 [11:0]
bits (stored into the DHR1[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHR1 (data holding registerx, which are internal non-
memory-mapped registers). The DHR1 register is then loaded into the DOR1 register either
automatically, by software trigger or by an external event trigger.
Figure 87. Data registers in single DAC channel mode
dac_ch1_trg2 tim2_trgo
Internal signal from on-chip
timers TIM2_TGO_CKTIM
dac_ch1_trg11 lptim1_out
Internal signal from on-chip
timers LPTIM1_OUT
dac_ch1_trg12 lptim2_out
Internal signal from on-chip
timers LPTIM2_OUT
dac_ch1_trg13 lptim3_out
Internal signal from on-chip
timers LPTIM3_OUT
dac_ch1_trg14 exti9 External pin EXTI[9]
Table 114. DAC interconnection (continued)
Signal name Source Source type
31 24 15 7 0
8-bit right aligned
12-bit left aligned
12-bit right aligned
ai14710b
To Next Page
Loading...
Need help?
General
