RM0453 Rev 5 1217/1450
RM0453 Low-power universal asynchronous receiver transmitter (LPUART)
1253
Idle line detection (WAKE = 0)
The LPUART enters Mute mode when the MMRQ bit is written to 1 and the RWU is
automatically set.
The LPUART wakes up when an Idle frame is detected. The RWU bit is then cleared by
hardware but the IDLE bit is not set in the LPUART_ISR register. An example of Mute mode
behavior using Idle line detection is given in Figure 338.
Figure 338. Mute mode using Idle line detection
Note: If the MMRQ is set while the IDLE character has already elapsed, the Mute mode is not
entered (RWU is not set).
If the LPUART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).
4-bit/7-bit address mark detection (WAKE = 1)
In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are
considered as data. In an address byte, the address of the targeted receiver is put in the 4
or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4-
bit/7-bit word is compared by the receiver with its own address which is programmed in the
ADD bits in the LPUART_CR2 register.
Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses
(ADD[5:0] and ADD[7:0]) respectively.
The LPUART enters Mute mode when an address character is received which does not
match its programmed address. In this case, the RWU bit is set by hardware. The RXNE
flag is not set for this address byte and no interrupt or DMA request is issued when the
LPUART enters Mute mode.
The LPUART also enters Mute mode when the MMRQ bit is written to ‘1’. The RWU bit is
also automatically set in this case.
The LPUART exits from Mute mode when an address character is received which matches
the programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE/RXFNE bit is set for the address character since the RWU bit has been
cleared.
Note: When FIFO management is enabled, when MMRQ bit is set while the receiver is sampling
the last bit of a data, this data may be received before effectively entering in Mute mode.
MSv31154V1
Data 1
Data 2 IDLEData 3 Data 4 Data 6
Idle frame detectedMMRQ written to 1
RWU
RX
Mute mode
Normal mode
RXNE RXNE
Data 5
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