RM0453 Rev 5 249/1450
RM0453 Power control (PWR)
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Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop 1,
Stop 2, Standby or Shutdown mode while the debug features are used. This is because the
CPU core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the CPU1
software can be debugged even when using the low-power modes extensively. For more
details, refer to Section 38.3.7: Serial-wire and JTAG debug port.
In Stop 0 and 1 modes, the EXTI CDBGPWRUPREQ wake-up event can be used to restart
the CPU clock by the debugger. For more details, refer to Section 16.3.1: EXTI wake-up
interrupt list.
6.5.1 Run mode
Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering the Sleep mode.
For more details, refer to RCC clock configuration register (RCC_CFGR).
Peripheral clock gating
In Run mode, HCLK and PCLK for individual peripherals and memories can be stopped at
any time to reduce the power consumption.
In Sleep mode, to further reduce the power consumption, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bits in the RCC_AHBxSMENR and RCC_APBxSMENR registers.
6.5.2 Low-power run mode (LPRun)
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the HCLK bus frequency must not exceed
2 MHz. HPRE, C2HPRE and SHDHPRE must be used to divide the SYSCLK frequency (or
MSI not exceeding 2 MHz must be used) before entering LPRun mode.
Warning: In LPRun mode, HSE32 cannot be used and must be disabled
before entering LPRun mode.
In LPRun mode HSI16 can be used as kernel clock for peripherals and PLL must be
disabled.
The device only enters LPRun mode once the low-power regulator is ready. The REGLPS
bit can be used to check that the low-power regulator is ready. The REGLPF bit must be
used to know if the device is in LPRun mode.
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