RM0453 Rev 5 239/1450
RM0453 Power control (PWR)
285
6.4 CPU2 boot
The CPU2 boot is controlled by the following sources:
• from C2BOOT bit in PWR control register 4 (PWR_CR4)
This allows the CPU1 to initialize the system after a reset or wake-up from system Low-
power mode, before booting the CPU2.
• when the system is secure (ESE = 1), from any illegal access wake-up event before
C2BOOT is set to 1 by the CPU1
This guarantees that the secure CPU2 is informed of any illegal access before it is
booted by C2BOOT.
Following reset, CPU2 is prevented from booting by the C2BOOT bit (except when booting
the device in RSS/SFI mode). Only once the CPU1 set the C2BOOT bit or if an illegal
access event is detected, CPU2 boots.
When exiting system low-power modes (Stop 0, 1, 2 or Standby), the CPU2 boot can be
controlled by the C2BOOT bit as follows:
• C2BOOT = 1: When exiting a system low-power mode, CPU2 boots when it is woken
up via a wake-up source.
• C2BOOT = 0: When exiting a system low-power mode, CPU2 is prevented from
booting, except when the system is secure and an illegal access wake-up event is
detected. On any CPU2 wake-up source other than an illegal access wake-up event,
CPU1 is woken up via a C2HF. It is then up to CPU1 to boot CPU2 by setting the
C2BOOT bit.
In a secure system, when booting the CPU2 due to an illegal access, the C2BOOTS flag
indicates so and the illegal access source is set in the ILAC status register. CPU2 keeps
booting due to an illegal access even after a system reset. However, in this case, the illegal
access source in the ILAC status register is cleared. The system stops booting the CPU2
due to an illegal access, only when the CPU2 enters CStop mode or after a POR reset.
When C2BOOT is set while the CPU2 has been boot due to an illegal access (C2BOOTS),
this illegal access boot must first be completed by having the CPU2 entering CStop mode.
This clears the illegal access boot mode and causes the CPU2 to restart in normal boot
mode.
To Next Page
Loading...
Need help?
General
