Embedded flash memory (FLASH) RM0453
128/1450 RM0453 Rev 5
4.9 Register access protection
The user option registers may be protected by security and privilege.
When the system is secure (ESE = 1) and the user option registers in the flash memory are
also protected by privileged (FLASH_PRIVMODER.PRIV = 1), the flash memory secure
user option bits (FSD, SFSA, BRSD, SBRSA, NBRSD, SNBRSA, SBRV, C2OPT, HDPAD,
HDPSA and DDS) are secure and privileged. They can be written only by the secure
privileged CPU2 and read by any CPU secure and non-secure, unprivileged and privileged.
When the CPU1 or the unprivileged CPU2 tries to write, the write is discarded and a flash
memory illegal access interrupt is generated.
When the system is secure (ESE = 1) and the user option bits in the flash memory are also
protected by privileged (FLASH_PRIVMODER.PRIV = 1), the other non-secure user option
bits are privileged. They can be written only by a privileged CPU1 or CPU2, and read by
CPU1, CPU2 unprivileged and privileged. On an unprivileged write access, the write is
discarded and a flash memory illegal access interrupt is generated.
Table 24: Register protection overview
Registers Security PRIVMODE
(1)
1. PRIVMODE privilege protection is only available when the device is secure ESE = 1.
FLASH_CxACR No No
FLASH_ACR2 Yes
(2)
2. Secure-privileged write access protected at any time, regardless of the device security ESE and
PRIVMODE values.
No
FLASH_KEYR No No
FLASH_OPTKEYR No No
FLASH_CxSR No No
FLASH_CxCR No No
FLASH_ECCR No No
FLASH_OPTR No Yes
FLASH_PCROP1xSR/ER No Yes
FLASH_WRP1xR No Yes
FLASH_IPCCBR No Yes
FLASH_SFR Yes
(3)
3. Secure write access protection is only applicable when the device is secure ESE = 1
Yes
FLASH_SRRVR Yes
(3)
Yes
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