Memory and bus architecture RM0453
62/1450 RM0453 Rev 5
This architecture is shown in the figure below.
Figure 1. System architecture
2.1.1 S0: CPU1 I-bus
This bus connects the instruction bus of the CPU1 core to the bus matrix. This bus is used
by the core to fetch instructions. The targets of this bus are the internal flash memory,
SRAM1and SRAM2.
2.1.2 S1: CPU1 D-bus
This bus connects the data bus of the CPU1 core to the bus matrix. This bus is used by the
core for literal load and debug access. The targets of this bus are the internal flash memory,
SRAM1 and SRAM2.
2.1.3 S2: CPU1 S-bus
This bus connects the system bus of the CPU1 core to the bus matrix. This bus is used by
the core to access data located in a peripheral or SRAM area. The targets of this bus are the
SRAM1, SRAM2, the AHB1 peripherals including the APB1 and APB2 peripherals, the
AHB2 peripherals and the AHB3 peripherals including the APB3.
2.1.4 S3: CPU2 S-bus
This bus connects the system bus of the CPU2 core to the bus matrix. This bus is used by
the core to fetch instructions, for literal load and debug access, and access data located in a
peripheral or SRAM area. The targets of this bus are the internal flash memory, SRAM1,
MSv60752V1
Bus matrix
SRAM1
FLASH
SRAM2
Flash
memory
arbiter
DMA1
AHB2
AHB3
DMA2
S0 S1 S2 S3 S4 S5
M0 M7M6M5M4M3M2M1
when remapped
AHB1
CPU1
Arm
Cortex-M4
CPU2
Arm
Cortex-M0+
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