RM0453 Rev 5 1395/1450
RM0453 Debug support (DBG)
1435
Refer to Section 38.8: CPU1 ROM table for the register boundary addresses.
38.11 CPU1 trace port interface unit (TPIU)
The TPIU formats the trace stream and outputs it on the external trace port signals. The
TPIU has one ATB slave ports for incoming trace data from the ITM. The trace port is the
serial-wire output, TRACESWO.
Figure 392 shows the TPIU architecture.
Figure 392. TPIU architecture
For more information on the TPIU, refer to the Arm
®
CoreSight™ SoC-400 Technical
Reference Manual [2.].
0xFE8
ITM_PIDR2
Res.
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REVISION
[3:0]
JEDEC
JEP106ID
[6:4]
Reset value 00111011
0xFEC
ITM_PIDR3
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REVAND[3:0] CMOD[3:0]
Reset value 00000000
0xFF0
ITM_CIDR0
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PREAMBLE[7:0]
Reset value 00001101
0xFF4
ITM_CIDR1
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CLASS[3:0]
PREAMBLE
[11:8]
Reset value 11100000
0xFF8
ITM_CIDR2
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PREAMBLE[19:12]
Reset value 00000101
0xFFC
ITM_CIDR3
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PREAMBLE[27:20]
Reset value 10110001
Table 280. CPU1 ITM register map and reset values (continued)
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSv60741V1
TPIU
Trace
output
(serializer)
ITM ATB
PPB
TRACESWO
APB
interface
Formatter
ATB
interface
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