RM0453 Rev 5 1371/1450
RM0453 Debug support (DBG)
1435
Refer to Section 38.8: CPU1 ROM table and Section 38.13: CPU2 ROM tables for the
register boundary addresses.
38.8 CPU1 ROM table
The ROM table is a CoreSight component that contains the base addresses of all the
CoreSight debug components accessible via the AHB-AP. This table allows a debugger to
discover the topology of the CoreSight system automatically.
There is one ROM table in the CPU1 sub-system. This table is pointed to by the AP_BASER
register in the CPU1 AHB-AP. It contains the base address pointer for the system control
space (SCS) registers, which allow the debugger to identify the CPU core, as well as the
FPB, DWT, and CTI.
The CPU1 ROM table (see Table 277) occupies a 4-Kbyte, 32-bit wide chunk of address
space, from 0xE00FF000 to 0xE00FFFFC.
0xFD0
CTI_PIDR4
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
F4KCOUNT
[3:0]
JEP106CON
[3:0]
Reset value 00000100
0xFD4to
0xFDC
Reserved Reserved
0xFE0
CTI_PIDR0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PARTNUM[7:0]
Reset value 00000110
0xFE4
CTI_PIDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
JEP106ID
[3:0]
PARTNUM
[11:8]
Reset value 10111001
0xFE8
CTI_PIDR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REVISION
[3:0]
JEDEC
JEP106ID
[6:4]
Reset value 01001011
0xFEC
CTI_PIDR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
REVAND[3:0] CMOD[3:0]
Reset value 00000000
0xFF0
CTI_CIDR0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[7:0]
Reset value 00001101
0xFF4
CTI_CIDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CLASS[3:0]
PREAMBLE
[11:8]
Reset value 10010000
0xFF8
CTI_CIDR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[19:12]
Reset value 00000101
0xFFC
CTI_CIDR3
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PREAMBLE[27:20]
Reset value 10110001
Table 276. CTI register map and reset values (continued)
Offset Register name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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