Sub-GHz radio (SUBGHZ) RM0453
176/1450 RM0453 Rev 5
For each access, the sub-GHz radio SPI NSS goes low at the start of the transfer and is set
high at the end, after all bytes have been transfered.
The following transaction types are supported:
• configuration transaction: provides the CPU with a direct access to control registers.
Used to write or read sub-GHz radio configuration registers or buffer memory.
• command transaction: requires more complex, non-atomic operations such as packet
transmission and reception or operating mode changes
BUSY is used to indicate the status of the sub-GHz radio and its ability (or not) to receive a
SPI transaction. Prior to issuing a new SPI transaction, the CPU must check the BUSY
status to make sure a new transaction can be received by the sub-GHz radio.
5.8.1 Sub-GHz radio command structure
The SPI command structure consists of an opcode and parameters when writing data to the
sub-GHz radio, and consists of a status when reading data.
In case of a write command that does not require any parameters, the CPU sent only an
opcode over the sub-GHz radio SPI interface.
In case of a write command that requires parameters, the opcode is followed immediately by
the parameter bytes. All parameters must be sent before the sub-GHz radio SPI NSS rising
edge, that terminates the command.
In case of a read command, the opcode is followed immediately by the status bytes. All
status must be received before the sub-GHz radio SPI NSS rising edge, that terminates the
command.
Command structure values are given in the table below.
5.8.2 Register and buffer access commands
Write_Register() command
Write_Register(Addr, Data0, Data1, to Datan) allows a block of bytes to be
written in a contiguous memory area, starting from the specified address. The address is
auto incremented after each byte.
Table 34. Command structure
Command type Byte 0 Byte 1:n
Write command without parameter Opcode Not applicable
Write command with parameters Opcode Parameters
Read command Opcode data
0123...n+3
Opcode Addr[15:0] Data0[7:0] ... Datan[7:0]
wwwwww
byte 0 bits 7:0 Opcode: 0x0D
bytes 2:1 bits 15:0 Addr[15:0]: first write address
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