STMicroelectronics STM32WL5 Series

RM0453 Rev 5 225/1450
RM0453 Sub-GHz radio (SUBGHZ)
227
5.10.59 Sub-GHz radio regulator drive control register
(SUBGHZ_REGDRVCR)
Address offset: 0x91F
Reset value: 0x08
This register is retained in Sleep mode but lost in Deep-Sleep mode.
5.10.60 Sub-GHz radio SMPS control 2 register (SUBGHZ_SMPSC2R)
Address offset: 0x923
Reset value: 0x06
This register is retained in Sleep mode but lost in Deep-Sleep mode.
76543210
Res Res Res Res TRIM[2:0 EN
rw rw rw rw
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:1 TRIM[2:0]: Regulator drive trimming
000: 1.22
001: 1.24
010: 1.26
011: 1.28
100: 1.30(default)
101: 1.32
110: 1.34
Bit 0 EN: Regulator drive enable
76543210
Res Res Res Res Res DRV[1:0] Res
rw rw
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:1 DRV[1:0]: SMPS maximum drive capability.
0x0: 20 mA
0x1: 40 mA
0x2: 60 mA
0x3: 100 mA (default)
Bit 0 Reserved, must be kept at reset value.