RM0453 Rev 5 263/1450
RM0453 Power control (PWR)
285
following alternative RTC clock sources can be selected by programming the RTCSEL[1:0]
bits in the RCC backup domain control register (RCC_BDCR):
• Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption.
• Low-power internal RC oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC oscillator is designed to add minimum power consumption.
To wake up from Stop mode with an RTC alarm event, it is necessary to:
• Configure the EXTI line 18 to be sensitive to rising edge.
• Configure the RTC to generate the RTC alarm.
To wake up from Standby mode, there is no need to configure the EXTI line 18.
To wake up from Stop mode with an RTC wake-up event, it is necessary to:
• Configure the EXTI line 20 to be sensitive to rising edge.
• Configure the RTC to generate the RTC alarm.
To wake up from Standby mode, there is no need to configure the EXTI line 20.
6.6 PWR registers
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
6.6.1 PWR control register 1 (PWR_CR1)
This register is reset after wake-up from Standby mode, except for bit field LPMS[2:0].
Access: additional APB cycles are used to access this register versus those used for a
standard APB access (three for a write and two for a read).
Address offset: 0x000
Reset value: 0x0000 0200
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. LPR Res. Res. Res. VOS[1:0] DBP Res. Res. FPDS FPDR
SUBGHZSPINSSSEL
LPMS[2:0]
rw rw rw rw rw rw rw rw rw rw
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