STMicroelectronics STM32WL5 Series User Manual

Power control (PWR) RM0453
254/1450 RM0453 Rev 5
The table below details how to exit the LPSleep mode.
6.5.7 Stop 0 mode
The Stop 0 mode is based on the CPU Deep-Sleep mode combined with the peripheral
clock gating. The voltage regulator is configured in main regulator mode. In Stop 0 mode, all
clocks in the V
CORE
domain are stopped.PLL, MSI, HSI16 and HSE32 oscillators are
disabled. Some peripherals with the wake-up capability (I2Cx (x = 1, 3), USARTx (x = 1, 2)
and LPUART1) can switch on HSI16 to receive a frame, and switch off HSI16 after receiving
the frame if it is not a wake-up frame. In this case, the HSI16 clock is propagated only to the
peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 0 mode. The consumption is increased when
thresholds higher than V
BOR0
are used.
The BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ULPEN bit of the PWR_CR3 register allows decreasing the current
consumption in this mode, but any drop of the voltage below the operating conditions
between two active periods of the supply detector results in a non-generation of PDR reset.
I/O states in Stop 0 mode
In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.
Table 50. LPSleep
LPSleep mode Description
Mode entry
LPSleep mode is entered from the LPRun mode.
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex system control register.
LPSleep mode is entered from the LPRun mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex system control register.
Mode exit
If WFI or return from ISR was used for entry
Interrupt: refer to Table 89: CPU1 vector table, and Table 90: CPU2 vector
table
If WFE was used for entry and SEVONPEND = 0:
Wake-up event: refer to Table 93: Wake-up interrupts
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 89: CPU1 vector table,
and Table 90: CPU2 vector table
Wake-up event: refer to Table 93: Wake-up interrupts
After exiting the LPSleep mode, the MCU is in LPRun mode.
Wake-up latency None

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English