RM0453 Rev 5 255/1450
RM0453 Power control (PWR)
285
Enter Stop 0 mode
The Stop 0 mode is entered according Section 6.5.3, when the SLEEPDEEP bit in the
Cortex system control register is set (see Table 51).
If flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
operation is completed.
If an access to the APB domain is ongoing, the Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its key register or by
hardware option. Once started, it cannot be stopped except by a reset. See
Section 30.3: IWDG functional description.
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC backup domain
control register (RCC_BDCR).
• Internal RC oscillator (LSI): this is configured by the LSIxON bit in the RCC
control/status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC
backup domain control register (RCC_BDCR).
• Sub-GHz radio activity, as programmed, see Section 5: Sub-GHz radio (SUBGHZ).
• PVD detection configured in PWR control register 3 (PWR_CR3).
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE: LPTIMx (x = 1, 2, 3), I2Cx (x = 1, 2, 3),
USARTx (x = 1, 2), LPUART1.
In Stop 0 mode, when HSIKERON is enabled, the wake-up capabilities of some peripherals
are also available when clocked by HSI16: I2Cx (x = 1, 2, 3), USARTx (x = 1, 2) or
LPUART1.
The comparators can be used in Stop 0 mode, PVM3 and PVD as well. If they are not
needed, they must be disabled by software to save their power consumption.
ADC, temperature sensor and VREFBUF buffer can consume power during the Stop 0
mode, unless they are disabled before entering this mode.
Exit Stop 0 mode
The Stop 0 mode is exited according to what is indicated in Section 6.5.4 (see Table 51 for
details).
When exiting Stop 0 mode by issuing an interrupt or a wake-up event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in RCC clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wake-up time is shorter when HSI16 is selected as wake-up system clock. The
MSI selection enables a wake-up at higher frequency, up to 48 MHz.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop 0 mode with HSI16. By keeping the internal regulator on
during Stop 0 mode, the consumption is higher but the startup time is reduced.
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