RM0453 Rev 5 301/1450
RM0453 Reset and clock control (RCC)
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7.2.17 Watchdog clock
If the independent watchdog (IWDG) is started by an hardware option or a software access,
the LSI clock is forced on.
If the LSI oscillator is disabled when starting the IWDG, the LSI oscillator is forced on. After
the LSI oscillator temporization, the clock is provided to the IWDG.
7.2.18 True RNG clock
The true random number generator (RNG) seed clock is derived from the MSI, from the PLL
output or from the LSE or LSI clock. It can reach 48 MHz and can be divided by a prescalers
values by configuring the true RNG register. It is asynchronous to the AHB clock.
7.2.19 Clock-out capability
• MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of the following clock signals can be selected as the MCO
clock:
– SYSCLK
–MSI
– HSI16 (only available when enabled by HSION)
– HSE32
– PLLRCLK
–LSI
–LSE
–PLLPCLK
– PLLQCLK
The selection is controlled by the MCOSEL[3:0] bits in the RCC clock configuration
register (RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] bits in
the RCC clock configuration register (RCC_CFGR).
The clock on MCO is only available in Run modes and is not available in Stop, Standby
and Shutdown modes.
• LSCO
Another output (LSCO) allows one of the following low-speed clocks to be output onto
the external LSCO pin:
–LSI
–LSE
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN bit in
the RCC backup domain control register (RCC_BDCR).
The clock on LSCO is available in Run, Stop, and Standby and Shutdown modes.
The configuration registers of the corresponding GPIO port must be programmed in
alternate function mode.
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