STMicroelectronics STM32WL5 Series User Manual

Global security controller (GTZC) RM0453
86/1450 RM0453 Rev 5
3.5.2 GTZC TZSC security configuration register
(GTZC_TZSC_SECCFGR1)
Address offset: 0x010
Reset value: 0x0000 0000
Secure write access only.
A bit of this register can be written only by a secure privileged transaction, when the
corresponding bit in GTZC_TZSC_PRIVCFGR1 is set to privileged. If unprivileged, the
register bit can be written by secure privileged and secure unprivileged transactions.
Read access is authorized for any type of transaction, secure/non-secure,
privileged/unprivileged.
An illegal access event on a privileged access is only generated when all peripheral register
bits in GTZC_TZSC_PRIVCFGR1 are configured as privileged.
When TZSC configuration is locked in GTZC_TZSC_CR.LCK, this register can no longer be
modified.
Note: When the system is non-secure (ESE = 0) this register cannot be written and is read zero.
Peripherals cannot be secured.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res.
PKA
SEC
Res. Res. Res. Res. Res. Res. Res. Res. Res.
RNG
SEC
AES
SEC
Res. Res.
rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 PKASEC: Secure access mode enabled for PKA
0: Non-secure
1: Secure
Bits 12:4 Reserved, must be kept at reset value.
Bit 3 RNGSEC: Secure access mode enabled for RNG
0: Non-secure
1: Secure
Bit 2 AESSEC: Secure access mode enabled for AES
0: Non-secure
1: Secure
Bits 1:0 Reserved, must be kept at reset value.

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English