RM0453 Rev 5 65/1450
RM0453 Memory and bus architecture
70
the flash memory contents can be accessed starting from address 0x0000 0000 or
0x0800 0000.
• Boot from system flash memory
The system flash memory is aliased in the CPU1 or CPU2 boot memory space at
address 0x0000 0000 and is also still accessible from its physical address 0x1FFF
0000.
• Boot from SRAM memory
The SRAM memory is aliased in the CPU1 boot memory space at address 0x0000
0000 and is also still accessible from its physical address 0x2000 0000.
CPU1 SRAM physical remap
Following CPU1 boot, the application software can modify the memory map at address
0x0000 0000. This modification is performed by programming the SYSCFG memory remap
register (SYSCFG_MEMRMP) in the SYSCFG controller.
The following memories can be remapped:
• Main flash memory
• System flash memory
• SRAM memory
Embedded bootloader
The embedded bootloader is located in the system flash memory, programmed by
STMicroelectronics during production. It is used to program the flash memory using one of
the following device interfaces:
• USART1 on pins PA9 and PA10
• USART2 on pins PA2 and PA3
• SPI1 on pins PA4, PA5, PA6 and PA7
• SPI2S2 on pins PB12, PB13, PB14 and PB15
The embedded bootloader runs on the CPU1 and can be used to load content in non-secure
memory areas.
Embedded secure firmware install and root security services
The embedded secure firmware install and root security services (SFI/RSS) are located in
the system flash memory, programmed by STMicroelectronics during production. They
allow programming of the flash memory with the same device interfaces than the ones used
by the embedded bootloader. The embedded SFI/RSS run on the CPU2 and can be used to
load content in secure and non-secure memory areas.
2.3 CPU2 boot
Following a device reset when CPU1 boots, CPU2 only boots after CPU1 has set the
C2BOOT bit in the power control register 4 (PWR_CR4). The C2BOOT value is retained in
Standby modes and CPU2 boots accordingly when exit from Standby.
CPU2 boots from its boot reset vector as defined by the flash memory user option C2OPT
and SBRV. CPU2 may boot from anywhere in user flash memory, SRAM1 or SRAM2.
To Next Page
Loading...
Need help?
General
