STMicroelectronics STM32WL5 Series User Manual

Memory and bus architecture RM0453
64/1450 RM0453 Rev 5
Values on BOOT0 and BOOT1 are latched after a reset. It is up to the user to provide the
correct value for the required boot mode.
BOOT0 and BOOT1 are also re-sampled when exiting Standby mode. Consequently they
must be kept in the required boot mode. After the startup delay, the CPU1 fetches the top-
of-stack from address 0x0000 0000, then starts code execution from the boot memory at
0x0000 0004.
Depending on the selected boot mode, main flash memory, system flash memory and
SRAM1 are accessible as follows:
• Boot from main flash memory
The main flash memory is aliased in the CPU1 boot memory space at address 0x0000
0000 and is also still accessible from its physical address 0x0800 0000. In other words,
1
x
0
1
0x
Yes
0 User flash boot SBRV boot
1 System flash boot SBRV boot
000
0
x
Hold SFI/RSS boot
(1)(2)(3)
1 Hold SBRV boot
(2)
1
1
0
x
System flash boot SBRV boot
0 0 SRAM1 boot SBRV boot
x x 1 User flash boot SBRV boot
11
x0
0x
Yes
0 User flash boot SBRV boot
1 System flash boot SBRV boot
01 0
0
x
Hold SFI/RSS boot
(1)(2)(3)
1 Hold SBRV boot
(2)
1
0
0
x
System flash boot SBRV boot
0 0 SRAM1 boot SBRV boot
x x 1 User flash boot SBRV boot
1. When engi bytes are invalid or PKA or AES is not available in the product, the SFI/RSS boot firmware installation is not
available.
2. Since CPU1 is kept in hold at reset boot, the system is not able to enter low-power modes (Stop, Standby or Shutdown).
3. Warning: If one of the user options FSD, BRSD, or NBRSD are set to "Security enable" or when RDP is not set to Level 0,
the device must not be boot in SFI/RSS mode.
Table 1. Device boot mode (continued)
Boot mode selection
Valid options
User flash empty
CPU1 aliasing space CPU2 boot
nBOOT1 option nBOOT0 option
PH3/BOOT0 nSWBOOT0
option
BOOT_LOCK
C2BOOT_LOCK

STMicroelectronics STM32WL5 Series Specifications

General

Brand	STMicroelectronics
Model	STM32WL5 Series
Category	Microcontrollers
Language	English