Inter-integrated circuit (I2C) interface RM0453
1112/1450 RM0453 Rev 5
34.7.11 I2C transmit data register (I2C_TXDR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: No wait states
34.7.12 I2C register map
The table below provides the I2C register map and reset values.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. TXDATA[7:0]
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 TXDATA[7:0]: 8-bit transmit data
Data byte to be transmitted to the I
2
C bus
Note: These bits can be written only when TXE = 1.
Table 238. I2C register map and reset values
Offset
Register
name
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0
I2C_CR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PECEN
ALERTEN
SMBDEN
SMBHEN
GCEN
WUPEN
NOSTRETCH
SBC
RXDMAEN
TXDMAEN
Res.
ANFOFF
DNF[3:0]
ERRIE
TCIE
STOPIE
NACKIE
ADDRIE
RXIE
TXIE
PE
Reset value 0000000000 000000 0 0 00000
0x4
I2C_CR2
Res.
Res.
Res.
Res.
Res.
PECBYTE
AUTOEND
RELOAD
NBYTES[7:0]
NACK
STOP
START
HEAD10R
ADD10
RD_WRN
SADD[9:0]
Reset value 00000000000000000000 0 0 0 0000
0x8
I2C_OAR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OA1EN
Res.
Res.
Res.
Res.
OA1MODE
OA1[9:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0
0xC
I2C_OAR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OA2EN
Res.
Res.
Res.
Res.
OA2MS
K [2:0]
OA2[7:1]
Res.
Reset value 0 0 0 0 0 0 0 0 0 0 0
0x10
I2C_
TIMINGR
PRESC[3:0]
Res.
Res.
Res.
Res.
SCLDEL
[3:0]
SDADEL
[3:0]
SCLH[7:0] SCLL[7:0]
Reset value 0000 00000000000000000 0 0 00000
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