RM0453 Rev 5 287/1450
RM0453 Reset and clock control (RCC)
371
In case on an internal reset, the internal pull-up R
PU
is deactivated in order to save the
power consumption through the pull-up resistor.
Figure 26. Simplified diagram of the reset circuit
Software reset
The SYSRESETREQ bit in CPU1 application interrupt and reset control register may be set
to force a software reset on the device (refer to the programming manual STM32 Cortex
®
-
M4 MCUs and MPUs (PM0214)).
The SYSRESETREQ bit in CPU2 application interrupt and reset control register may be set
to force a software reset on the device.
Low-power mode security reset
To prevent that critical applications mistakenly enter a low-power mode, two low-power
mode security resets are available.
If enabled in option bytes, the resets are generated in the following conditions:
• Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in
user option bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
• Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in user
option bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.
• Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in
user option bytes. In this case, whenever a Shutdown mode entry sequence is
successfully executed, the device is reset instead of entering Shutdown mode.
For further information on the user option bytes, refer to Section 4.4.1: Option bytes
description.
Option byte loader reset
The option byte loader reset is generated when the OBL_LAUNCH bit is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.
MSv62602V1
External
reset
V
DD
R
PU
WWDG reset
Radio protocol error reset
(1)
CPU1 software reset
Low-power manager reset
IWDG reset
Option byte loader reset
BOR reset
Pulse
generator
(min 20 ȝs)
NRST
System reset
Filter
CPU2 software reset
1) The sub-GHz radio protocol error reset is available in non LoRa devices only, STM32WL54xx.