RM0453 Rev 5 1083/1450
RM0453 Inter-integrated circuit (I2C) interface
1113
SMBus alert
The SMBus ALERT optional signal is supported. A slave-only device can signal the host
through the SMBALERT# pin that it wants to talk. The host processes the interrupt and
simultaneously accesses all SMBALERT# devices through the alert response address
(0b0001 100). Only the device(s) which pulled SMBALERT# low acknowledges the alert
response address.
When configured as a slave device(SMBHEN = 0), the SMBA pin is pulled low by setting the
ALERTEN bit in the I2C_CR1 register. The Alert Response Address is enabled at the same
time.
When configured as a host (SMBHEN = 1), the ALERT flag is set in the I2C_ISR register
when a falling edge is detected on the SMBA pin and ALERTEN = 1. An interrupt is
generated if the ERRIE bit is set in the I2C_CR1 register. When ALERTEN = 0, the ALERT
line is considered high even if the external SMBA pin is low.
If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if
ALERTEN = 0.
Packet error checking
A packet error checking mechanism has been introduced in the SMBus specification to
improve reliability and communication robustness. The packet error checking is
implemented by appending a packet error code (PEC) at the end of each message transfer.
The PEC is calculated by using the C(x) = x
8
+ x
2
+ x + 1 CRC-8 polynomial on all the
message bytes (including addresses and read/write bits).
The peripheral embeds a hardware PEC calculator and allows a not acknowledge to be sent
automatically when the received byte does not match with the hardware calculated PEC.
Timeouts
This peripheral embeds hardware timers in order to be compliant with the three timeouts
defined in SMBus specification.
Table 231. SMBus timeout specifications
Symbol Parameter
Limits
Unit
Min Max
t
TIMEOUT
Detect clock low timeout 25 35
mst
LOW:SEXT
(1)
1. t
LOW:SEXT
is the cumulative time a given slave device is allowed to extend the clock cycles in one message
from the initial START to the STOP. It is possible that, another slave device or the master also extends the
clock causing the combined clock low extend time to be greater than t
LOW:SEXT
. Therefore, this parameter is
measured with the slave device as the sole target of a full-speed master.
Cumulative clock low extend time (slave device) - 25
t
LOW:MEXT
(2)
2. t
LOW:MEXT
is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device
or another master also extends the clock, causing the combined clock low time to be greater than t
LOW:MEXT
on a given byte. Therefore, this parameter is measured with a full speed slave device as the sole target of
the master.
Cumulative clock low extend time (master device) - 10
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