General-purpose timers (TIM16/TIM17) RM0453
902/1450 RM0453 Rev 5
Figure 246. Update rate examples depending on mode and TIMx_RCR register
settings
27.3.4 Clock selection
The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Edge-aligned mode
UEV
Update Event: preload registers transferred to active registers
and update interrupt generated.
Counter
TIMx_CNT
TIMx_RCR = 0 UEV
TIMx_RCR = 1 UEV
TIMx_RCR = 2 UEV
TIMx_RCR = 3 UEV
TIMx_RCR = 3
and
re-synchronization UEV
(by SW)
Upcounting
MS31084V2
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