Power control (PWR) RM0453
252/1450 RM0453 Rev 5
6.5.5 Sleep mode
I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Enter Sleep mode
The Sleep mode is entered from Run mode according to Enter low-power mode, when the
SLEEPDEEP bit in the CPU system control register is cleared (see Table 49).
Exit Sleep mode
The MCU exits the Sleep mode (see Table 49) as indicated in Exit low-power mode.
Table 48. CPU wake-up versus system operating mode
System
mode
CPU1 CPU2
CPU1 wake-up CPU2 wake-up
C1SBF
C1STOPxF
C2SBF
C2STOPxF
Run
0 0 0 0 Wake-up from Run Wake-up from Run
0100
Wake-up from Stop, but system is
already in Run due to CPU2
Wake-up from Run
0001Wake-up from Run
Wake-up from Stop, but system is
already in Run due to CPU1
1000
Wake-up from Standby, but system is
already in Run due to CPU2
Wake-up from Run
0010Wake-up from Run
Wake-up from Standby, but system is
already in Run due to CPU1.
1100
Wake-up from Standby followed by Stop,
but system is already in Run due to
CPU2
Wake-up from Run
0011Wake-up from Run
Wake-up from Standby followed by Stop,
but system is already in Run due to
CPU1
Stop
(1)
0 1 0 1 Wake-up from Stop (CPU2 still in CStop) Wake-up from Stop (CPU1 still in CStop)
1101
Wake-up from Stop after the system has
been in Standby (CPU2 still in CStop)
Wake-up from Stop (CPU1 still in CStop)
0 1 1 1 Wake-up from Stop (CPU2 still in CStop)
Wake-up from Stop after the system
having been in Standby (CPU1 still in
CStop).
Standby 1 0 1 0
Wake-up from Standby (CPU2 still in
CStop)
Wake-up from Standby (CPU1 still in
CStop)
N/A Others Not valid, does not occur
1. Wake-up from Stop 0 and 1 or Stop 2 mode can be detected by the corresponding CnSTOPF and
CnSTOP2F.