Inter-integrated circuit (I2C) interface RM0453
1068/1450 RM0453 Rev 5
Figure 287. Transfer sequence flow for slave receiver with NOSTRETCH = 1
Figure 288. Transfer bus diagrams for I2C slave receiver
(mandatory events only)
MS19856V2
Slave initialization
Slave reception
Read I2C_RXDR.RXDATA
I2C_ISR.STOPF
=1?
No
Yes
I2C_ISR.RXNE
=1?
Yes
No
Set I2C_ICR.STOPCF
MS19857V4
A
ADDR
AA
RXNE
A
RXNE
RXNE
EV1 EV2 EV3
A
AA A
RXNE
RXNE
EV4
Example I2C slave receiver 3 bytes, NOSTRETCH = 1:
S
Address data 1 data 2 data 3
P
Example I2C slave receiver 3 bytes, NOSTRETCH = 0:
S
Address data1 data2 data3
EV3
EV2
EV1
RXNE RXNE RXNE
EV2: RXNE ISR: rd data1
EV4: RXNE ISR: rd data3
EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
EV3: RXNE ISR: rd data2
EV1: RXNE ISR: rd data1
EV3: RXNE ISR: rd data3
EV2: RXNE ISR: rd data2
Transmission
Reception
SCL stretch
Legend
Legend
Transmission
Reception
SCL stretch