EasyManuals Logo

STMicroelectronics STM32WL5 Series User Manual

STMicroelectronics STM32WL5 Series
1450 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #560 background image
Analog-to-digital converter (ADC) RM0453
560/1450 RM0453 Rev 5
The AWD comparison is performed at the end of each ADC conversion. The
ADC_AWDx_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the
comparison.
As ADC_AWDx_OUT is generated by the ADC_CLK domain and AWD flag is generated by
the APB clock domain, the rising edges of these signals are not synchronized.
Figure 77. ADC_AWDx_OUT signal generation
Figure 78. ADC_AWDx_OUT signal generation (AWDx flag not cleared by software)
MSv45362V1
EOC FLAG
ADC STATE
RDY
AWDx FLAG
Conversion1
outside
ADC_AWDx_OUT
inside
Cleared
by SW
Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
outsideinside outside outside inside
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7
Cleared
by SW
Cleared
by SW
Cleared
by SW
MSv45363V1
EOC FLAG
ADC STATE
RDY
AWDx FLAG
Conversion1
outside
ADC_AWDx_OUT
inside
not cleared by SW
Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
outsideinside outside outside inside
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the STMicroelectronics STM32WL5 Series and is the answer not in the manual?

STMicroelectronics STM32WL5 Series Specifications

General IconGeneral
BrandSTMicroelectronics
ModelSTM32WL5 Series
CategoryMicrocontrollers
LanguageEnglish

Related product manuals